/****************************************************************************
 * clkgate_tb.v
 ****************************************************************************/

`include "../risc_t16_i_core/clkgate.v"

/**
 * Module: clkgate_tb
 * 
 * 门控时钟
 */
`timescale 1ns / 10ps

module clkgate_tb;

    localparam 	PERI    =   10;

    reg   clk_in;
    reg   clk_en;
    wire  clk_out;
	

    clkgate clkgate_inst
    (
        .clk_in(clk_in),
        .clk_en(clk_en),
        .clk_out(clk_out)
    );


    always #(PERI/2) clk_in = ~clk_in;

    initial 
    begin

        $dumpfile("clkgate_tb.vcd");
        $dumpvars(0, clkgate_tb);

        clk_in      = 1'b0;
        clk_en      = 1'b0;

        #48 clk_en = 1'b1;

        #50 clk_en = 1'b0;

        #50 $finish;
    end
    
endmodule